Last week we covered gas turbines. The week before, photonics testing. This week the bottleneck is about etching equipment.

When most people picture how an advanced chip gets made, they picture one machine: the EUV lithography system from ASML.

You see that giant, bus-sized machine that uses light too fine to see to print circuit patterns onto silicon. While that machine is crucial, it’s not the only important one.

Lithography is one step in a sequence of hundreds required to make the transistors on a chip. The steps that add and remove material around it matter just as much, and get far less attention.

And one of them, selective etching, is where a real chokepoint is now forming, just as the industry makes its biggest architectural change in more than a decade.

A transistor is just a tiny switch. A modern chip packs billions of them, and computing is those switches flipping on and off. Two parts matter here:

Making chips faster means making these transistors smaller, so more fit in the same space. But as the channel shrinks, the gate struggles to shut it off cleanly, and current seeps through even when the switch should be off, leaking power, throwing off heat.

So the real challenge at each new generation isn't just shrinking the transistor. It's also keeping the gate in firm enough control of the channel that "off" still means off.

For more than a decade, the answer has been a transistor shape called the FinFET. Instead of laying the channel flat, where the gate can only press from the top, you stand it up off the wafer like a thin fin and fold the gate over it, gripping three sides at once.

A three-sided pinch instead of one gives far firmer control, which is exactly what you need as the channel shrinks. It was a great solution and FinFET carried the industry all the way down to the 3nm generation.

But below 3nm it runs out of room. Pushing toward 2nm and beyond, the channel gets so small that even a three-sided grip leaves a gap. The bottom, where the fin meets the wafer, is the one side the gate can't reach, and that's where current leaks. For the next generation, the industry needs a new transistor entirely, one the gate can grip on every side.

That new shape is gate-all-around, or GAA, and the name says it. If gripping three sides was good, grip all four i.e. wrap the gate completely around the channel, leaving no uncovered side for current to slip through. Total control, and room to keep shrinking.

The catch is how you build it.

To wrap the gate the whole way around, the channel can't rest on the wafer anymore because whatever it sits on blocks the underside. It has to be lifted off the surface and suspended, with empty space all around, so the gate can be threaded underneath as well as on top. And since one tiny suspended channel barely carries current, you don't build one, instead you build a stack of ultra-thin silicon sheets, called "nanosheets," one above the next, each with the gate wrapped fully around it.

That suspended stack is something a FinFET never needed, and building it demands process steps and equipment that a FinFET line didn't, which is a new way to grow the stack, and a new, unusually delicate way to carve it apart (etch).

And it isn't one company's bet. The entire leading edge is crossing to GAA at the same time.

While most of these are 2nm, it doesn't stop there. Each node ahead stacks more sheets and demands still more of the same difficult steps, with the AI buildout pulling underneath it all. Every new generation of GPUs and custom accelerators wants more leading-edge wafers, which means more GAA transistors. Total wafer-equipment spending is now tracking north of $140 billion for the year, revised up mid-cycle as the orders kept coming.

To understand where that new step fits, let's take a step back and quickly see how a chip gets built in the first place. The front end, which is the part of manufacturing where the transistors are formed on the wafer, runs as a loop. The same short cycle of steps, repeated eighty to a hundred-plus times, once per layer, to stack the chip up.

A simplified version of that cycle looks like this:

So lithography draws the pattern but etch carves it.

Most of that etching simply transfers a pattern. But a subset does something harder i.e. selective etching. This is removing one material while leaving another, sitting right beside it, untouched. For most of chipmaking's history this was a useful tool among many. GAA is what changes its status.

Those suspended nanosheet stack we talked about earlier, the way you build it is to grow it as a solid block first, in alternating layers, almost like a club sandwich. A sheet of silicon (a channel-to-be), then a filler layer of silicon-germanium, then silicon again, and so on.

Then you reach in and dissolve away only the filler, leaving the silicon sheets suspended, with gaps where the filler was, ready for the gate to wrap around. That dissolving step is the new one. It's called channel release, and it is a selective etch where it has to eat away the silicon-germanium filler while leaving the silicon sheets, a few atoms away, completely untouched.

That is the whole difficulty. The two materials are chemical cousins, so coaxing the etch to devour one and ignore the other takes extraordinary precision. Push it a touch too far and you thin a channel, collapse a sheet, or kill the switch. The FinFET had nothing like it.

So with GAA, along with a few other processes, selective etching goes from minor to critical.

The equipment that build chips come from only a handful of companies worldwide. Deposition and etch tools, from fewer still. And for the most advanced selective etch steps required at leading edge, it is mainly made by just 3 companies:

For the GAA-specific selective etch in particular, Lam holds the lead, with the largest share of gate-all-around etch wins as the node qualified and a long history of dominance in exactly this kind of removal. Applied Materials is the close challenger with the broadest overall portfolio. Tokyo Electron is the distant third.

Both leaders are pouring money into capacity and the numbers they're putting up show why.

One caveat: these are company-wide figures, not only selective-etch line items. Lam's billion, for instance, spans etch and deposition together. What makes channel-release the chokepoint is that almost no one else can make it, and the chip fails without it.

And the capacity can't just be willed into being. These are harder machines with new chemistries, extreme selectivity, atomic-layer precision, co-developed with each chipmaker. Tools take time to qualify, lead times run past a year, and the real gate is the customer's clean-room and fab readiness that dictates how fast anything gets installed.

Which leaves the honest question for the stocks. Lam and Applied Materials are worth hundreds of billions already, and much of the current GAA adoption is already priced in.

But the tailwind usually compounds. Every node from 2nm to 1.4nm and below stacks more sheets and more of these steps, pulled by each new generation of AI accelerators. A yield stumble or capex air-pocket could slow it but with a demand curve this steep, the case for more upside is real.

Pays rent: The leading-edge foundries racing into GAA like TSMC, Samsung, Intel.

Captures rent: Lam Research, Applied Materials, and Tokyo Electron, the only three that build leading-edge etch tools. Lam leads the GAA-specific selective etch.

A few important earnings this week. Read our post and pre-call briefs here and stay prepared.

No major earnings calls this week, so we're sending you back to last week's, where Micron put up a quarter nobody's model was ready for.

The Street sat around $36B. We called it above consensus at $39.5B and Micron still made us look cautious, printing a record $41.5B at nearly 85% gross margins, then guiding next quarter to a whopping $50B.

But the big number was the easy part. The signals that move the next two quarters were buried deeper in the call. We took them apart in our post-call breakdown.

Want the live data behind The Chokepoint?

This issue, we named Lam, Applied Materials, and Tokyo Electron as the etch chokepoint.

In Tessara terminal, you can pull the live tightening on etch and deposition, see which of 400+ public names are most exposed, and read the Micron post-call. We called Micron at $39.5B while the Street sat at $36B. It printed $41.5B.

“From extensive sector and company deep dives to thoughtful market updates, it has become a go-to resource for our investment team” - Portfolio Manager, Titan Global Capital Management

See the terminal →

See you next week,

Teng & Arvind

This article is for informational and research purposes only. It is not financial advice, investment advice, or a recommendation to buy or sell any security. Tessara Research does not publish price targets. The views expressed here reflect our analysis at the time of publication and may change as new evidence arrives. Readers should do their own research and consult a qualified financial adviser before making investment decisions.