Last week we covered power transformers. The week before, ABF substrates. This week the bottleneck moving to silicon photonics testing.
Over the past few years, AI data centers have started to push copper to its limits.
Copper still works well over short distances, like inside a server or a rack. But when you need to move huge amounts of data across rows of GPUs, between switches, or between buildings, copper starts to struggle. It uses too much power, creates too much heat.
So the industry is moving more of the network to light.
That is where silicon photonics comes in. These are chips that help move data using light instead of just electrical signals.
A few editions back we covered one bottleneck in that scale-up: indium phosphide (InP), which is the scarce material inside the lasers doing the work.
This week, we are looking at another constraint that’s forming a few steps downstream in the photonics build out.
Testing: Catching faults before they get expensive
A GPU, a CPU or any AI accelerator doesn’t get shipped until it's been tested, repeatedly.
The reason is pure economics. A faulty chip that slips through gets more expensive to catch at every step it survives.
So testing happens in stages, each one catching what the last one missed. A simplified flow of these stages looks like this:
Wafer test: Chips are checked while still on the wafer, which are the silicon disc they're built on, before being cut into individual chips. Bad ones get flagged here, where they're cheapest to discard.
Burn-in: The survivors get stress tested in increased heat and power for hours, to force out the units that work today but would die in their first weeks of use. Pass this and you're a "known-good" die (or KGD) i.e. safe to build into something bigger.
Package and system test: The finished, packaged chip gets tested again, then tested a third time inside the full system along with other packaged components.
The whole philosophy is to catch the fault as early and as cheaply as possible. The cost of finding a bad chip rises can be >10x at each later stage of packaging. Catch it on the wafer, and you've thrown away a few dollars. Catch it in the system, and you've scrapped an assembly worth thousands.
Semiconductor testing has been a tightening constraint over the past few weeks. (Source: Tessara)
Testing photonics is a different problem
The optical chips or dies going into all this new networking gear follow a similar path of testing. But two things make them harder.
First, you can't test light the way you test electricity at the wafer level. A standard tester checks electrical behaviour. An optical chip has to be checked on its light. The right wavelength, the right power, the right signal quality, etc. This requires purpose-built equipment most test houses simply don't own.
Second, the burn-in step requires more power. Newer generations of silicon photonics devices can require much more power during testing and stabilization than earlier versions. Some testing companies have said these devices may need 2-4x more power per wafer than previous generations. That means the equipment has to deliver and manage much more energy across thousands of tiny photonic devices on a wafer at the same time.
For years, none of this was a real bottleneck. But with the rise in demand for silicon photonics, testing is becoming critical.
CPO changes the math
Until recently, the optics lived in removable plugs on the front of the switch. If one failed, a technician swapped it in minutes without taking the switch down. A bad optic was cheap to fix in the field, so you could afford to catch failures late.
Co-packaged optics (CPO) ends that. The whole point is to move the optics off the front panel and set them right next to the main switch chip, inside the same package.
Shorter distances, far less power, far more bandwidth. It's where NVIDIA, Broadcom, and the hyperscalers are all heading.
But there's a trade. Once the optical chip is bonded into that package, you can't pull it out, and rework is limited. A failure now means replacing the entire switch, which means hours of downtime instead of minutes.
That inverts the economics of testing.
When a late failure is cheap, you can catch problems at the package or system stage. When a late failure means scrapping a switch worth tens of thousands of dollars, you can't. You have to catch the bad optical chip on the wafer, at burn-in, before it's ever built in.
Co-packaging pushes the entire burden of reliability back onto wafer-level burn-in and makes it mandatory.
Which raises the obvious question: who can actually do that?
One company does this at scale
One company is unusually exposed to this constraint: Aehr Test Systems (AEHR)
AEHR price shot up after announcing a major silicon photonics customer in March
It sells test and burn-in systems, and its FOX platform is one of the few publicly visible solutions already shipping for high-power, wafer-level burn-in of silicon photonics devices.
Optical chips need reliability screening before they are sealed into costly modules. Doing that at wafer level means failures can be caught earlier, before packaging cost is added. AEHR’s FOX-XP platform can burn in multiple wafers in parallel, giving it a throughput advantage in a market where photonic wafers can contain large numbers of small die.
AEHR is not the only semiconductor test company, and adjacent players like Advantest, Teradyne, FormFactor and others operate around wafer-level test. But in the specific niche of high-power, multi-wafer burn-in for silicon photonics production, AEHR appears to have a rare, proven, already-qualified position.
That advantage is starting to show up in bookings:
Bookings are inflecting ahead of revenue: In the recent quarter, Aehr reported booked orders of $37.2M (up over 500% from the prior quarter), a book-to-bill above 3.5x and ended the quarter with a $38.7M backlog. CEO Gayn Erickson tied the surge directly to strong AI and data-center infrastructure demand.
A new photonics customer just signed on: In March, Aehr added a major silicon photonics customer, with orders running from qualification through high-volume production.
The demand wave behind it is enormous: Co-packaged optics is barely shipping today, and volume isn't expected until 2027. But it's coming fast. Goldman Sachs now sees the AI optical-networking market growing roughly tenfold, from ~$15B in 2026 to ~$154B by 2028, with CPO alone contributing about $91B of that.
Source: X (@aleabitoreddit)
What to watch
AEHR's next earnings: The whole thesis is the order book, so watch it. Specifically: any language about its lead optical customer moving from qualification into volume production, and whether new silicon photonics customers are added.
The photonics makers' earnings: Photonics players like Coherent (COHR) and Lumentum (LITE), Applied Optoelectronics (AAOI), etc. Listen for anything about qualification, reliability screening, or burn-in capacity. That's where demand for Aehr's machines shows up first.
The Week Ahead
A few important earnings this week. Read our post and pre-call briefs here and stay prepared.
Earnings Tab on Tessara
Wednesday, June 10
ORCL (Oracle) — Hyperscaler. Watch: Q1 capex cadence vs $18.6B prior quarter
Want the live data behind The Chokepoint? Tessara is the research terminal for the AI buildout. We track what's binding in the supply chain and what it means for what you own. 300+ companies across compute, memory, foundry, networking, and power.
See you next week,
Teng & Arvind
This article is for informational and research purposes only. It is not financial advice, investment advice, or a recommendation to buy or sell any security. Tessara Research does not publish price targets. The views expressed here reflect our analysis at the time of publication and may change as new evidence arrives. Readers should do their own research and consult a qualified financial adviser before making investment decisions.